Phase-locked loop (“PLL”) circuits are well known in the art and are often used for frequency multiplication. As shown in FIG. 1, the main components of a PLL circuit 10 for multiplying a reference signal 12's frequency by N comprise a phase comparator 14, a low-pass filter 16, a voltage control oscillator (“VCO”) 18 and an N frequency divider module 20. The N frequency divider module 20 provides feedback control to provide a correct frequency comparison with the reference signal 12 in the phase comparator 14. The N frequency divider module 20 supplies the phase comparator 14 with a feedback signal obtained by N-dividing an output signal 22 from the VCO 18. The phase comparator 14 provides an error signal to the low-pass filter 16 corresponding to a phase difference between the reference signal 12 and the rising (or falling) edge of the feedback signal from the N frequency divider module 20. The low-pass filter 16 extracts only the DC components from the error signal output from the phase comparator 14 and generates a control voltage 24 for controlling the oscillation frequency of the VCO 18. The VCO generates the output signal 22, whose frequency is N times as high as that of the reference signal 12.
While the PLL design of FIG. 1 offers flexibility for frequency multiplication, it does suffer from some significant disadvantages. One disadvantage of the prior art design is that the VCO operating frequency can become very high (depending on the value of N required), resulting in increased power consumption for the multiplier circuit. Further, a VCO circuit is a complex analog device, requiring techniques for reducing power noise and frequency jitter, a common problem with PLL designs. Applications requiring very high frequencies might also use a prior art PLL circuit for frequency multiplication, but in order to increase the frequencies beyond the range of a single PLL circuit, a second PLL circuit may be required. This solution involves not only the problems described above for PLL circuits in general, but also the increased cost associated with the additional circuit real estate needed for the additional PLL circuit. The use of multiple PLL circuits is thus not a desired solution because of cost and complexity.
Prior art frequency multiplier circuits must perform a 90 degree phase shift to create a 90 degree phase signal from the reference signal prior to performing the frequency multiplication. This is because in order to double the frequency of a reference signal, a Sine/Cosine signal pair for the frequency of interest must first be generated (hence the 90 degree phase shift). If the sinusoidal reference signal has a frequency θ, the sine of θ can be determined simply from the original signal. However, when the frequency of the reference signal is doubled, the sine of 2*θ is given by: Sin(2θ)=2*Sin(θ)*Cos(θ). Thus, to multiply the reference signal frequency (e.g., to double the reference signal frequency), a 90 degree phase shift signal must first be generated. The reference differential signal cannot be used directly to perform the frequency multiplication. As a result, prior art frequency multiplication circuits are complex and costly, and require additional techniques for reducing power noise and frequency jitter. Thus, a circuit for frequency multiplication without the use of a PLL is desirable.
Therefore, a need exists for a frequency multiplier and amplification circuit that can reduce or eliminate these problems and others associated with prior art frequency multiplier circuits.